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functional block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 l r ck wclk bclk dgnd1 dv dd 1 rdedge s/ m 384/ 256 av dd v in l capl1 capl2 agndl v ref l clkin tag sout dv dd 2 reset msbdly r l just agnd v in r capr1 capr2 agndr v ref r serial output interface three-stage fir decimation filter dgnd2 three-stage fir decimation filter clock divider voltage reference dac single-to- differential input converter single-to- differential input converter ad1870 dac dac dac rev. a a single-supply 16-bit - stereo adc features single 5 v power supply single-ended dual-channel analog inputs 92 db (typ) dynamic range 90 db (typ) s/(thd + n) 0.006 db decimator pass-band ripple fourth order, 64 oversampling - modulator three-stage, linear-phase decimator 256 f s or 384 f s input clock less than 100 w (typ) power-down mode input overrange indication on-chip voltage reference flexible serial output interface 28-lead soic package applications consumer digital audio receivers digital audio recorders, including portables cd-r, dcc, md, and dat multimedia and consumer electronics equipment sampling music synthesizers ad1870 * shapes the o ne-bit comparator? quantization noise out of the audio pass band. the high order of the modulator randomizes the modulator o utput, reducing idle tones in the ad1870 to very low levels. because its modulator is single bit, the ad1870 is inherently monotonic and has no mechanism for producing differential lin earity errors. the input section of the ad1870 uses autocalibration to correct any dc offset voltage present in the circuit, provided that the inputs are ac-coupled. the single-ended dc input voltage can swing between 0.7 v and 3.8 v typically. the ad1870 antialias input circuit requires four external 470 pf npo ceramic chip filter capacitors, two for each channel. no active electronics are needed. decoupling capacitors for the supply and reference pins are also required. the dual-digital decimation filters are triple-stage, finite impulse response filters for effectively removing the modulators high frequency quantization noise and reducing the 64 f s single-bit output data rate to an f s word rate. they provide linear phase and a narrow transition band that properly digitizes 20 khz sig nals at a 44.1 khz sampling frequency. pass-band ripple is less than 0.006 db, and stop-band attenuation exceeds 90 db. ( continued on page 7) information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 product overview the ad1870 is a stereo, 16-bit oversampling adc based on sigma-delta ( - ) technology intended primarily for digital audio bandwidth applications requiring a single 5 v power supply. each sin gle-ended channel consists of a fourth order one-bit noise shaping modulator and a digital decimation filter. an on-chip voltage reference, stable over temperature and time, defines the full-scale range for both channels. digital output data from both channels are time multiplexed to a single, flexible serial inter- face. the ad 1870 accepts a 256 f s or a 384 f s input clock (f s is the sampling frequency) and operates in both serial port master and slave modes. in slave mode, all clocks must be ex- ternally derived from a common source. input signals are sampled at 64 f s onto internally buffered switched capacitors, eliminating external sample-and-hold ampli- fiers and minimizing the requirements for antialias filtering at the input. with simplified antialiasing, linear phase can be preserved across the pass band. the on-chip single-ended-to-differential sig- nal c onverters save the board designer from having to provide them externally. the ad1870? internal differential architecture provides increased dynamic range and excellent power supply rejection characteristics. the ad1870? proprietary fourth order differential switched-capacitor - modulator architecture * prote cted by u.s. patent numbers 5055843, 5126653; others pend ing.
ad1870?pecifications rev. a ? test conditions unless otherwise noted supply voltages 5.0 v ambient temperature 25 c input clock (f clkin ) [256 f s ] 12.288 mhz input signal 991.768 hz ?.5 db full scale measurement bandwidth 23.2 hz to 19.998 khz load capacitance on digital outputs 50 pf input voltage hi (v ih ) 2.4 v input voltage lo (v il ) 0.8 v master mode, data i 2 s-justified (refer to figure 14). device under test (dut) bypassed and decoupled as shown in figure 3. dut is antialiased and ac-coupled as shown in figure 2. dut is calibrated. values in bold typeface are tested; all others are guaranteed but not tested. analog performance min typ max unit resolution 16 bits dynamic range (20 hz to 20 khz, ?0 db input) without a-weight filter 89 93 db with a-weight filter 92 96 db signal to (thd + noise) 86.5 90.5 db signal to thd 94 db analog inputs single-ended input range ( full scale) * v ref 1.49 v input impedance at each input pin 32 k ? v ref 2.05 2.25 2.55 v dc accuracy gain error 0.5 2.5 % interchannel gain mismatch 0.05 db gain drift 115 ppm/ c midscale offset error (after calibration) 3 20 lsbs midscale drift ?.2 lsb/ c crosstalk (eiaj method) ?10 ?00 db * v in p-p = v ref 1.326. minimum input v v maximum input v v ref ref ref ref = =+ ? ? ? ? ? ? ? ? ? ? ? ? . . 1 326 2 1 326 2
digital i/o min typ max unit input voltage hi (v ih ) 2.4 v input voltage lo (v il ) 0.8 v input leakage (i ih @ v ih = 5 v) 10 a input leakage (i il @ v il = 0 v) 10 a output voltage hi (v oh @ i oh = 2 ma) 2.4 v output voltage lo (v ol @ i ol = 2 ma) 0.4 v input capacitance 15 pf digital timing (guaranteed over 40 c to +85 c, dv dd = av dd = 5 v 5%. refer to figures 17 19.) min typ max unit t clkin clkin period 48 81 780 ns f clkin clkin frequency (1/t clkin ) 1.28 12.288 20.48 mhz t cpwl clkin lo pulsewidth 15 ns t cpwh clkin hi pulsewidth 15 ns t rpwl reset lo pulsewidth 50 ns t bpwl bclk lo pulsewidth 15 ns t bpwh bclk hi pulsewidth 15 ns t dlyckb clkin rise to bclk xmit (master mode) 15 ns t dlyblr bclk xmit to l r ck transition (master mode) 15 ns t dlybwr bclk xmit to wclk rise 10 ns t dlybwf bclk xmit to wclk fall 10 ns t dlydt bclk xmit to data/tag valid (master mode) 10 ns t setlrbs l r ck setup to bclk sample (slave mode) 10 ns t dlylrdt l r ck transition to data/tag valid (slave mode) no msb delay mode (for msb only) 40 ns t setwbs wclk setup to bclk sample (slave mode) data position controlled by wclk input mode 10 ns t dlybdt bclk xmit to data/tag valid (slave mode) all bits except msb in no msb delay mode all bits in msb delay mode 40 ns power min typ max unit supplies voltage, analog and digital 4.75 5 5.25 v analog current 43 52 ma analog current power-down (clkin running) 25 a digital current 9.3 12 ma digital current power-down (clkin running) 50 a dissipation operation both supplies 263 315 mw operation analog supply 216 260 mw operation digital supply 47 55 mw power-down both supplies (clkin running) 375 w power-down both supplies (clkin not running) 375 w power supply rejection (see tpc 5) 1 khz 300 mv p-p signal at analog supply pins 90 db 20 khz 300 mv p-p signal at analog supply pins 68 db stop band (>0.55 f s ) any 300 mv p-p signal 110 db ad1870 rev. a ?
temperature range min typ max unit specifications guaranteed +25 c functionality guaranteed 40 +85 c storage 60 +100 c digital filter characteristics min typ max unit decimation factor 64 pass-band ripple 0.006 db stop-band * attenuation 90 db 48 khz f s (at recommended crystal frequencies) pass band 0 21.6 khz stop band 26.4 khz 44.1 khz f s (at recommended crystal frequencies) pass band 0 20 khz stop band 24.25 khz 32 khz f s (at recommended crystal frequencies) pass band 0 14.4 khz stop band 17.6 khz other f s pass band 0 0.45 f s stop band 0.55 f s group delay 36/f s s group delay variation 0 s * stop band repeats itself at multiples of 64 f s , where f s is the output word rate. thus the digital filter will attenuate to 0 db across the frequency spectrum except for a range 0.55 f s wide at multiples of 64 f s . specifications subject to change without notice. absolute maximum ratings min typ max unit dv dd 1 to dgnd1 and dv dd 2 to dgnd2 0 +6 v av dd to agnd/agndl/agndr 0 +6 v digital inputs dgnd 0.3 dv dd + 0.3 v analog inputs agnd 0.3 av dd + 0.3 v agnd to dgnd 0.3 +0.3 v reference voltage indefinite short circuit to ground soldering (10 sec) +300 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1870 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ? rev. a ordering guide package package model temperature description option ad1870ar 40 c to +85 c soic r-28 ad1870ar reel 40 c to +85 c soic r-28 in 13 reel (1000 pcs.) eval-ad1870eb evaluation board ad1870
ad1870 rev. a ? pin function descriptions input/ pin pin output name description 1 i/o l r ck left/ right clock 2 i/o wclk word clock 3 i/o bclk bit clock 4i dv dd 1 5 v digital supply 5 i dgnd1 digital ground 6 i rdedge read edge polarity select 7i s/ m slave/ master select 8 i 384/ 256 clock mode 9i av dd 5 v analog supply 10 i v in l left channel input 11 o capl1 left external filter capacitor 1 12 o capl2 left external filter capacitor 2 13 i agndl left analog ground 14 o v ref l left reference voltage output 15 o v ref r right reference voltage output 16 i agndr right analog ground 17 o capr2 right external filter capacitor 2 18 o capr1 right external filter capacitor 1 19 i v in r right channel input 20 i agnd analog ground 21 i r l just right/ left justify 22 i msbdly delay msb one bclk period 23 i reset reset 24 i dgnd2 digital ground 25 i dv dd 2 5 v digital supply 26 o sout serial data output 27 o tag serial overrange output 28 i clkin master clock definitions dynamic range the ratio of a full-scale output signal to the integrated output noise in the pass band (20 hz to 20 khz), expressed in decibels (db). dynamic range is measured with a 60 db input signal and is equal to (s/(thd + n)) 60 db. note that spurious harmonics are below the noise with a 60 db input, so the noise level establishes the dynamic range. the dynamic range is specified with and with- out an a-weight filter applied. signal to total harmonic distortion + noise (s/(thd + n)) the ratio of the root-mean-square (rms) value of the fundamen- tal input signal to the rms sum of all other spectral components in the pass band, expressed in decibels. signal to total harmonic distortion (s/thd) the ratio of the rms value of the fundamental input signal to the rms sum of all harmonically related spectral components in the pass band, expressed in decibels. pass band the region of the frequency spectrum unaffected by the attenu- ation of the digital decimator s filter. pass-band ripple the peak-to-peak variation in amplitude response from equal- amplitude input signal frequencies within the pass band, expressed in decibels. stop band the region of the frequency spectrum attenuated by the digi- tal decimator s filter to the degree specified by stop-band attenuation. gain error with a near full-scale input, the ratio of actual output to expected output, expressed as a percentage. interchannel gain mismatch with identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels. gain drift change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per c. midscale offset error output response to a midscale dc input, expressed in least significant bits (lsbs). midscale drift change in midscale offset error with a change in temperature, expressed as parts-per-million (ppm) per c. crosstalk (eiaj method) ratio of response on one channel with a grounded input to a full-scale 1 khz sine wave input on the other channel, expressed in decibels. power supply rejection with no analog input, signal present at the output when a 300 mv p-p signal is applied to the power supply pins, ex- pressed in decibels of full scale. group delay intuitively, the time interval required for an input pulse to appear at the converter s output, expressed in milliseconds (ms). more precisely, the derivative of radian phase with respect to radian frequency at a given frequency. group delay variation the difference in group delays at different input frequencies. specified as the difference between the largest and smallest group delays in the pass band, expressed in microseconds ( s).
ad1870 rev. a ? 24 2 022 20 18 16 14 12 10 8 6 4 frequency ?khz 0 ?40 ?0 ?20 ?00 ?0 ?0 ?0 dbf s tpc 1. 1 khz tone at 0.5 dbfs (16 k-point fft) 0 140 24 80 120 2 100 0 20 60 40 22 20 18 16 14 12 10 8 6 4 frequency khz dbfs tpc 2. 1 khz tone at 10 dbfs (16 k-point fft) frequency khz dbfs 80 100 20 94 98 2 96 0 88 92 90 86 84 82 18 16 14 12 10 8 6 4 tpc 3. thd + n vs. frequency at 0.5 dbfs input amplitude dbfs dbfs 80 100 94 98 96 60 88 92 90 86 84 82 0.5 50 40 30 20 10 tpc 4. thd + n vs. input amplitude at 1 khz frequency khz dbfs 60 100 20 95 2 0 80 90 85 75 70 65 18 16 14 12 10 8 6 4 tpc 5. power supply rejection to 300 mv p-p on av dd frequency khz dbfs 80 20 115 2 120 0 100 105 95 90 85 18 16 14 12 10 8 6 4 110 tpc 6. channel separation vs. frequency at 0.5 dbfs typical performance characteristics
ad1870 rev. a 7 ( continued from page 1 ) the flexible serial output port produces data in two s complement, msb-first format. the input and output signals are ttl compa tible. the port is configured by pin selections. each 16-bit output word of a stereo pair can be formatted within a 32-bit field of a 64-bit frame as either right-justified, i 2 s compatible, word clock c ontrolled, or left-justified positions. both 16-bit samples can also be packed into a 32-bit frame, in left-justified and i 2 s compatible positions. the ad1870 is fabricated on a single monolithic integrated circuit using a 0.5 m cmos double polysilicon, double metal process and is offered in a plastic 28-lead soic package. analog and digital supply connections are separated to isolate the analog circuitry from the digital supply and reduce digital crosstalk. the ad1870 operates from a single 5 v power supply over the temperature range of 40 c to +85 c and typically consumes less than 260 mw of power. theory of operation - modulator noise shaping the stereo, internally differential, analog modulator of the ad1870 employs a proprietary feedforward and feedback archi- tecture that passes input signals in the audio band with a unity transfer function yet simultaneously shapes the quantization noise generated by the one-bit comparator out of the audio band (see figure 1). without the - architecture, this quanti- zation noise would be spread uniformly from dc to one-half the oversampling frequency, 64 f s . dac dac single-to- differential converter modulator bitstream output v in v in v in figure 1. modulator noise shaper (one channel) - architectures shape the quantization noise-transfer function in a nonuniform manner. through careful design, this transfer function can be specified to high-pass filter the quantization noise out of the audio band into higher frequency regions. the ad1870 also incorporates a feedback resonator from the fourth integrator s output to the third integrator s input. this resona- tor does not affect the signal transfer function but allows the flexible placement of a zero in the noise transfer function for more effective noise shaping. oversampling by 64 simplifies the implementation of a high performance audio analog-to-digital conversion system. antialias requirements are minimal; a single pole of filtering will usually suffice to eliminate inputs near f s and its higher multiples. a fourth order architecture was chosen both to strongly shape the noise out of the audio band and to help break up the idle tones produced in all - architectures. these architectures have a tendency to generate periodic patterns with a constant dc input, a response that looks like a tone in the frequency domain. these idle tones have a direct frequency dependence on the input dc offset and an indirect dependence on temperature and time as it affects the dc offset. the ad1870 suppresses idle tones 20 db or better below the integrated noise floor. the ad1870 s modulator was designed, simulated, and ex- haustively tested to remain stable for any input within a wide tolerance of its rated input range. the ad1870 is designed to internally reset itself should it ever be overdriven, to prevent it from going unstable. it will reset itself within 5 s at a 48 khz sampling frequency after being overdriven. overdriving the inputs will produce a waveform clipped to plus or minus full scale. see tpcs 1 through 6 for illustrations of the ad1870 s typical analog performance as measured by an audio precision system one. signal-to-(distortion + noise) is shown under a range of conditions. note that there is a small variance between the ad1870 analog performance specifications and some of the performance plots. this is because the audio precision system one measures thd and noise over a 20 hz to 24 khz band- width, while the analog performance is specified over a 20 hz to 20 khz bandwidth (i.e., the ad1870 performs slightly better than the plots indicate). the power supply rejection graph (tpc 5) illustrates the benefits of the ad1870 s internal differential ar- chitecture. the excellent channel separation shown in tpc 6 is the result of careful chip design and layout. digital filter characteristics the digital decimator accepts the modulator s stereo bit stream and simultaneously performs two operations on it. first, the decimator low-pass filters the quantization noise that the modu- lator shaped to high frequencies and filters any other out-of- audio-band input signals. second, it reduces the data rate to an output word rate equal to f s . the high frequency bit stream is decimated to stereo 16-bit words at 48 khz (or other desired f s ). the out-of-band one-bit quantization noise and other high frequency components of the bit stream are attenuated by at least 90 db. the ad1870 decimator implements a symmetric finite impulse response (fir) filter that possesses a linear phase response. this filter achieves a narrow transition band (0.1 f s ), high stop-band attenuation (>90 db), and low pass-band ripple (<0.006 db). the narrow transition band allows the unattenu- ated digitization of 20 khz input signals with f s as low as dbfs 0 80 1.0 60 70 0.1 0.0 40 50 30 20 10 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 110 90 100 normalized f s 120 10 tpc 7. digital filter signal transfer function to f s
ad1870 rev. a 8 44.1 khz. the stop-band attenuation is sufficient to eliminate modulator quantization noise from affecting the output. low pass-band ripple prevents the digital filter from coloring the audio signal. see tpc 7 for the digital filter s characteristics. the output from the decimator is available as a single serial output, multiplexed between left and right channels. note that the digital filter itself is operating at 64 f s . as a consequence, nyquist images of the pass-band, transition band, and stop band will be repeated in the frequency spectrum at multiples of 64 f s . thus the digital filter will attenuate to greater than 90 db across the frequency spectrum, except for a window 0.55 f s wide centered at multiples of 64 f s . any in- put signals, clock noise, or digital noise in these frequency windows will not be attenuated to the full 90 db. if the high frequency signals or noise appear within the pass-band images within these windows, they will not be attenuated at all, and input antialias filtering should therefore be applied. sample delay the sample delay or group delay of the ad1870 is dominated by the processing time of the digital decimation filter. fir filters convolve a vector representing time samples of the input with an equal-sized vector of coefficients. after each convolution, the input vector is updated by adding a new sample at one end of the pipeline and discarding the oldest input sample at the other. for a fir filter, the time at which a step input appears at the output will be when that step input is halfway through the input sample vector pipeline. the input sample vector is updated every 64 f s . the equation that expresses the group d elay for the ad1870 is: group delay ( sec ) = 36/ f s ( hz ) for the most common sample rates, this can be summarized as: f s group delay 48 khz 750 s 44.1 khz 816 s 32 khz 1125 s due to the linear phase properties of fir filters, the group delay variation, or differences in group delay at different frequencies, is essentially zero. operating features voltage reference and external filter capacitors the ad1870 includes a 2.25 v on-board reference that deter- mines the ad1870 s input range. the left and right reference pins (pin 14 and pin 15) should be bypassed with a 0.1 f ceramic chip capacitor in parallel with a 4.7 f tantalum as shown in figure 3. note that the chip capacitor should be clos- est to the pin. the internal reference can be overpowered by applying an external reference voltage at the v ref l (pin 14) and v ref r (pin 15) pins, allowing multiple ad1870s to be calibrated to the same gain. it is not possible to overpower the left and right re ference pins individually; the external reference voltage should be applied to both pin 14 and pin 15. note that the ref- erence pins must still be bypassed as shown in figure 3. while it is possible to bypass each reference pin (v ref l and v ref r) with a capacitor larger than the suggested 4.7 f, it is not recommended. a larger capacitor will have a longer charge-up time, which may extend into the autocalibration period, yielding incorrect results. the ad1870 requires four external filter capacitors on pins 11, 12, 17, and 18. these capacitors are used to filter the single-to- differen tial converter outputs and are too large for pr actical integration onto the die. they should be 470 pf npo ceramic chip type capacitors, as shown in figure 3, placed as close to the ad1870 package as possible. sample clock an external master clock supplied to clkin (pin 28) drives the a d1870 modulator, decimator, and digital in terface. as with any analog-to-digital conversion system, the sampling clock must be low jitter to prevent conversion errors. if a crystal oscil- lator is used as the clock source, it sh ould be bypassed with a 0.1 f capacitor, as shown below in figure 3. for the ad1870, the input clock operates at either 256 f s or 384 f s as selected by the 384/ 256 pin. when 384/ 256 is hi, the 384 mode is selected; when 384/ 256 is lo, the 256 mode is selected. in both cases, the clock is divided down to obtain the 64 f s clock required for the modulator. the output word rate itself will be at f s . this relationship is illustrated for popular sample rates below: 256 mode 384 mode modulator output word clkin clkin sample rate rate 12.288 mhz 18.432 mhz 3.072 mhz 48 khz 11.2896 mhz 16.9344 mhz 2.822 mhz 44.1 khz 8.192 mhz 12.288 mhz 2.048 mhz 32 khz the ad1870 serial interface will support both master and slave modes. note that in slave mode it is required t hat the serial interface clocks be externally derived from a common source. in master mode, the serial interface clock outputs are internally derived from clkin. reset, autocalibration, and power-down the active lo reset pin (pin 23) initializes the digital deci- mation filter and clears the output data buffer. while in the reset state, all digital pins defined as outputs of the ad1870 are driven to ground (except for bclk, which is driven to the state defined by rdedge (pin 6)). analog devices recommends resetting the ad1870 on initial power-up so that the device is properly calibrated. the reset signal must remain lo for the minimum period specified in the specifications section. the reset pulse is asynchronous with respect to the master clock, clkin. if, however, multiple ad1870s are used in a system, and it is desi red that they leave the reset state at the same time, the common reset pulse should be made synchronous to clkin (i.e., reset should be brought hi on a clkin falling edge). multiple ad1870s can be synchronized to each other by using a single master clock and a single reset signal to initialize all devices. on coming out of reset, all ad1870s will begin sam- pling at the same time. note that in slave mode, the ad1870 is inactive (and all outputs are static, including wclk) until the first rising edge of l r ck after the first falling edge of l r ck. this initial low going then high going edge of l r ck can be used to skew the sampling start-up time of one ad1870 relative to other ad1870s in a system. in the data position con- trolled by the wclk input mode, wclk m ust be hi with l r ck hi, then w clk hi with l r ck lo, then w clk hi with l r ck hi before the ad1870 starts sampling.
ad1870 rev. a 9 the ad1870 achieves its specified performance without the need for user trims or adjustments. this is accomplished through the use of on-chip automatic offset calibration that takes place immediately following reset. this procedure nulls out any off- sets in the single-to-differential converter, the analog modulator, and the decimation filter. autocalibration completes in approxi- mately 8192 (1/(f l r ck ) seconds and need only be pe rformed once at power-up in most applications. (in slave mode, the 8192 cycles required for autocalibration do not start until after the first rising edge of l r ck following the first falling edge of l r ck.) the autocalibration scheme assumes that the inputs are ac-coupled. dc-c oupled inputs will work with the ad1870, but the autocalibration algorithm will yield an incorrect offset compensation. the ad1870 also features a power-down mode. it is enabled by the active lo reset pin 23 (i.e., the ad1870 is in power- down mode while reset is held lo). the power savings are specified in the specifications section. the converter is shut down in the power-down state and will not perform conversions. the ad1870 will be reset upon leaving the power-down state, and autocalibration will commence after the reset pin goes hi. power consumption can be further reduced by slowing down the master clock input (at the expense of input pass band width). note that a minimum clock frequency, f clkin , is specified for the ad1870. tag overrange output the ad1870 includes a tag serial output (pin 27) that is pro- vided to indicate status on the level of the input voltage. the tag output is at ttl compatible logic levels. a pair of unsigned binary bits are output, synchronous with l r ck (msb then lsb), that indicate whether the current signal being converted is: more than 1 db under full scale, within 1 db under full scale, within 1 db over full scale, or more than 1 db over full sc ale. the timing for the tag output is shown in figures 7 16. note that the tag bits are not sticky ; i.e., they are not peak read- ing, but rather change with every sample. decoding of these two bits is as follows: tag bits msb lsb meaning 0 0 more than 1 db under full scale 0 1 within 1 db under full scale 1 0 within 1 db over full scale 1 1 more than 1 db over full scale application issues recommended input structure the ad1870 input structure is single-ended to allow the board designer to achieve a high level of functional integration. the very simple recommended input circuit is shown in figure 2. note the 1 f ac-coupling capacitor, which allows input level shifting for 5 v only operation and for autocalibration to properly null offsets. the 3 db point of the single-pole antialias rc filter is 240 khz, which results in essentially no attenuation at 20 khz. attenuation at 3 mhz is approximately 22 db, which is adequate to suppress f s noise modulation. if the analog inputs are exter- nally ac-coupled, the 1 f ac-coupling capacitors shown in figure 2 are not required. ad1870 v in r v in l left input right input 300 2.2nf npo 1 f 300 2.2nf npo 1 f figure 2. recommended input structure for externally dc-coupled inputs analog input voltage swing the single-ended input range of the analog inputs is specified in relative terms in the specifications section. the input level at which clipping occurs linearly tracks the voltage reference level; i.e., if the reference is high relative to the typical 2.25 v, the allowable input range without clipping is correspondingly wider, and if the reference is low relative to the typical 2.25 v, the allowable input range is correspondingly narrower. thus the maximum input voltage swing can be computed using the following ratio: 225 2 983 .( ) .( ) () () v nominal reference voltage v p p nominal voltage swing x v measured referenc voltage y v maximum swing without clipping ? = e
ad1870 rev. a 10 layout and decoupling considerations obtaining the best possible performance from the ad1870 requires close attention to board layout. adhering to the follow- ing principles will produce typical values of 92 db dynamic range and 90 db s/(thd + n) in target systems. schematics and lay- out artwork of the ad1870 evaluation board, which implement these recommendations, are available from analog devices. the principles and their rationales are listed below. the first two pertain to bypassing and are illustrated in figure 3. 5v analog 5v digital 5v digital ad1870 capl2 capl1 clkin agnd av dd dv dd 1 dgnd1 dgnd2 dv dd 2 470pf npo agndl v ref lv ref r agndr capr2 capr1 470pf npo oscillator 5v digital 10nf 470pf npo 470pf npo 10nf 1 f 0.1 f 1 f 1 f 0.1 f 4.7 f 0.1 f 4.7 f 0.1 f figure 3. recommended bypassing and oscillator circuits there are two pairs of digital supply pins on opposite sides of the part (pins 4 and 5 and pins 24 and 25). the user should tie a bypass chip capacitor (10 nf ceramic) in parallel with a decou- pling capacitor (1 f tantalum) on each pair of supply pins as close to the pins as possible. the traces between these package pins and the capacitors should be as short and as wide as pos- sible. this will prevent digital supply current transients from being inductively transmitted to the inputs of the part. use a 0.1 f chip analog capacitor in parallel with a 1.0 f tantalum capacitor from the analog supply (pin 9) to the analog ground plane. the trace between this package pin and the capacitor should be as short and as wide as possible. the ad1870 should be placed on a split ground plane. the digital ground plane should be placed under the top end of the package, and the analog ground plane should be placed under the bottom end of the package as shown in figure 4. the split should be between pins 8 and 9 and between pins 20 and 21. the ground planes should be tied together at one spot under- neath the center of the package with an approximately 3 mm trace. this ground plane technique also minimizes rf transmis- sion and reception. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 l r ck wclk bclk dgnd1 dv dd 1 rdedge s/ m 384/ 256 av dd v in l capl1 capl2 agndl v ref l clkin tag sout dv dd 2 reset msbdly r l just agnd v in r capr1 capr2 agndr v ref r dgnd2 digital ground plane analog ground plane figure 4. recommended ground plane each reference pin (pin 14 and pin 15) should be bypassed with a 0.1 f ceramic chip capacitor in parallel with a 4.7 f tantalum capacitor. the 0.1 f chip cap should be placed as close to the package pin as possible, and the trace to it from the reference pin should be as short and as wide as possible. keep this trace away from any analog traces (pins 10, 11, 12, 17, 18, 19). cou- pling between input and reference traces will cause even order harmonic distortion. if the reference is needed somewhere else on the printed circuit board, it should be shielded from any signal dependent traces to prevent distortion. wherever possible, minimize the capacitive load on the digital outputs of the part. this will reduce the digital spike currents drawn from the digital supply pins and help keep the ic sub- strate quiet. how to extend snr a cost-effective method of improving the dynamic range and snr of an analog-to-digital conversion system is to use multiple ad1870 channels in parallel with a common analog input. this technique makes use of the fact that the noise in independent modulator channels is uncorrelated. thus every doubling of the number of ad1870 channels used will improve the system dy- namic range by 3 db. the digital outputs from the correspond- ing deci-mator channels must be arithmetically averaged to obtain the improved results in the correct data format. a micro- processor, either general purpose or dsp, can easily perform the averaging operation.
ad1870 rev. a 11 figure 5 shows a circuit for obtaining a 3 db improvem ent in dynamic range by using both channels of a single ad 1870 with a mono input. a stereo implementation would req uire using two ad1870s and using the recommended input structure shown in figure 2. note that a single micropro cessor would likely be able to handle the averaging requirements for both left and right channels. ad1870 recommended input buffer single channel input digital averager ad1870 v in r v in l single channel output figure 5. increasing dynamic range by using two ad1870 channels digital interface modes of operation the ad1870 s flexible serial output port produces data in two s-complement, msb-first format. the input and output signals are ttl logic-level compatible. time multiplexed serial data is output on sout (pin 26), left channel then right chan- nel, as determined by the left/right clock signal l r ck (pin 1). note that there is no method for forcing the right channel to precede the left channel. the p ort is configured by pin selections. the ad1870 can operate in either master or slave mode, with the data in right-justified, i 2 s compatible, word clock controlled, or left-justified positions. the various mode options are pin programmed with the s/ m (slave/ master ) pin (7), the right/ left justify pin (21), and the msbdly pin (22). the function of these pins is summarized below. s/ m r l just msbdly wclk bclk l r ck serial port operation mode 1 1 1 output input input slave mode. wclk frames the data. the msb is output on the 17th bclk cycle. provides right-justified data in slave mode with a 64 f s bclk frequency. see figure 7. 1 1 0 input input input slave mode. the msb is output in the bclk cycle after wclk is detected hi. wclk is sampled on the bclk active edge, with the msb valid on the next bclk active edge. tying wclk hi results in i 2 s-justified data. see figure 8. 1 0 1 output input input slave mode. data left-justified with wclk framing the data. wclk rises immediately after an l r ck transition. the msb is valid on the first bclk active edge. see figure 9. 1 0 0 output input input slave mode. data i 2 s-justified with wclk framing the data. wclk rises in the second bclk cycle after an l r ck transi- tion. the msb is valid on the second bclk active edge. see figure 10. 0 1 1 output output output master mode. data right-justified. wclk frames the data, going hi in the 17th bclk cycle. bclk frequency = 64 f s . see figure 11. 0 1 0 output output output master mode. data right-justified + 1. wclk is pulsed in the 17th bclk cycle, staying hi for only 1 bclk cycle. bclk frequency = 64 f s . see figure 12. 0 0 1 output output output master mode. data left-justified. wclk frames the data. bclk frequency = 64 f s . see figure 13. 0 0 0 output output output master mode. data i 2 s-justified. wclk frames the data. bclk frequency = 64 f s . see figure 14.
ad1870 rev. a 12 serial port data timing sequences the rdedge input (pin 6) selects the bit clock (bclk) polarity. rdedge hi causes data to be transmitted on the bclk falling edge and valid on the bclk rising edge; rdedge lo causes data to be transmitted on the bclk rising edge and valid on the bclk falling edge. this is shown in the serial data output timing diagrams. the term sampling is used generically to denote the bclk edge (rising or falling) on which the serial data is valid. the term transmitting is used to denote the other bclk edge. the s/ m input (pin 7) selects slave mode (s/ m hi) or master mode (s/ m lo). note that in slave mode, bclk may be continuous or gated, i.e., a stream of pulses during the data phase followed by periods of inactivity between channels. in the master modes, the bit clock (bclk), the left/right clock (l r ck), and the word clock (wclk) are always outputs, gen- erated inte rnally in the ad 1870 from the master clock (clkin) input. in master mode, a l r ck cycle defines a 64-bit frame. l r ck is hi for a 32-bit field and l r ck is lo for a 32- bit field. in the slave modes, the bit clock (bclk) and the left/right clock (l r ck) are user-supplied inputs. the word clock ( wclk) is an internally generated output, except when s/ m is hi, r l just is hi, and msbdly is lo when it is a user-supplied input that controls the data position. note that the ad1870 does not sup- port asynchronous operation in slave mode; the clocks (clkin, l r ck, bclk, and wclk) must be externally derived from a common source. in general, clkin should be divided down externally to create l r ck, bclk, and wclk. in the slave modes, the relationship between l r ck and bclk is not fixed to the extent that there can be an arbitrary number of bclk cycles between the end of the data transmission and the next l r ck transition. the slave mode timing diagrams are therefore simplified as they show precise 32-bit fields and 64-bit frames. in two slave modes, it is possible to pack two 16-bit samples in a single 32-bit frame, as shown in figures 15 and 16. bclk, l r ck, data, and tag operate at one-half the frequency (twice the period) as in the 64-bit frame modes. this 32-bit frame mode is enabled by pulsing the l r ck hi for a mini- mum of one bclk period to a maximum of 16 bclk periods. the l r ck hi for one bclk period case is shown in figures 15 and 16. with a one or two bclk period hi pulse on l r ck, note that both the left and right tag bits are output immedi- ately, back to back. with a three-to-sixteen bclk pe riod hi pulse on l r ck, the left tag bits are followed by one to fourteen dead cycles, i.e., zeros, followed by the right tag bits. also note that wclk stays hi continuously when the ad1870 is in the 32-bit frame mode. figure 15 illustrates the left-justified case, while figure 16 illustrates the i 2 s-justified case. in all modes, the left and right channel data is updated with the next sample within the last 1/8 of the current conversion cycle, i.e., within the last four bclk cycles in 32-bit frame mode, and within the last eight bclk cycles in 64-bit frame mode. the user must cons train the output timing such that the msb of the right channel is read before the final 1/8 of the current con- version pe riod. two modes deserve special discussion. the first special mode, slave mode, data position controlled by wclk input (s/ m = hi, r l just = hi, msbdly = lo), shown in figure 8, is the only mode in which wclk is an input. the 16-bit output data-words can be placed at user-defined loca- tions within 32-bit fields. the msb will appear in the bclk period after wclk is detected hi by the bclk sampling edge. if wclk is hi du ring the first bclk of the 32-bit field, i.e, if wclk is tied hi, then the msb of the output word will be valid on the sampling edge of the second bclk. the effect is to delay the msb for one bit clock cycle into the field, making the output data compatible at the data format level with the i 2 s data format. note that the relative placement of the wclk input can v ary from 32-bit field to 32-bit field, even within the same 64-bit frame. for example, within a single 64-bit frame, the left word could be right-justified (by pulsing wclk hi on the 16th bc lk) and the right word could be in an i 2 s compat- ible data format (by having wclk hi at the beginning of the sec- ond field). in the second special mode, master mode, right-justified with msb delay, wclk pulsed in 17th bclk cycle (s/ m = lo, r l just = hi, msbdly = lo), shown in figure 12, wclk is an output and is pulsed for one cycle by the ad1870. the msb is valid on the 18th bclk sampling edge, and the lsb extends into the first bclk period of the next 32-bit field.
ad1870 rev. a 13 timing parameters for master modes, a bclk transm itting edge (labeled xmit ) will be delayed from a clkin rising edge by t dlyckb , as shown in figure 17. a l r ck transition will be delayed from a bclk transmitting edge by t dlyblr . a wclk rising edge will be delayed from a bclk transmitting edge by t dlybwr , and a wclk falling edge will be delayed from a bclk transmitting edge by t dlybwf . the data and tag outputs will be delayed from a transmitting edge of bclk by t dlydt . for slave modes, an l r ck transition must be set up to a bclk sampling edge (labeled sample ) by t setlrbs (see figure 18). the data and tag outputs will be delayed from an l r ck transition by t dlylrdt , and data and tag outputs will be delayed from bclk tr ansmitting edge by t dlybdt . for slave mode, data position controlled by wclk input, wclk must be set up to a bclk sampling edge by t setwbs . for both master and slave modes, bclk must have a mini- mum lo pulsewidth of t bpwl and a minimum hi pulsewidth of t bpwh . the ad1870 clkin and reset timing is shown in figure 19. clkin must have a minimum lo pulsewidth of t cpwl and a minimum hi pulsewidth of t cpwh . the minimum period of clkin is given by t clkin . reset must have a minimum lo pulsewidth of t rpwl . note that there are no setup or hold time requirements for reset . master clock (clkin) considerations it is recommended that the bclk and l r ck are derived from clkin to ensure correct phase relationships. the modulator of the ad1870 runs at 64 f s . therefore, best performance is obtained when the bclk rate equals 64 f s or 32 f s . bclk rates such as 48 f s may result in an increased spectral noise floor, depending on the phase relationship of bclk to clkin. synchronizing multiple ad1870s multiple ad1870s can be synchronized by making all the ad1870s serial port slaves. this option is illustrated in f igure 6. see the reset, autocalibration, and power-down section for additional information. #1 ad1870 slave mode clkin data bclk wclk l r ck clock source #2 ad1870 slave mode clkin data bclk wclk l r ck #n ad1870 slave mode clkin data bclk wclk l r ck reset reset reset figure 6. synchronizing multiple ad1870s
ad1870 rev. a 14 bclk rdedge = lo bclk rdedge = hi 31 32 1 2 15 16 17 18 19 32 1 2 15 16 17 18 19 32 1 2 msb-14 lsb previous data msb-1 left data msb-2 lsb right data sout output zeros zeros msb-1 msb-2 lsb zeros wclk output tag output msb lsb left tag msb lsb right tag msb lsb left tag l r ck input input msb msb figure 7. serial data output timing: slave mode, right-justified with no msb delay, s/m = hl, rljust = hl, msbdly = hl bclk rdedge = lo bclk rdedge = hi msb-1 left data msb-2 lsb sout output zeros right data msb-1 msb-2 lsb zeros wclk input tag output msb left tag msb right tag zeros 1234 17 1234 17 input l r ck input msb lsb msb lsb figure 8. serial data output timing: slave mode, data position controlled by wclk input, s/ m = hl, r l just = hl, msbdly = lo bclk rdedge = lo bclk rdedge = hi 31 32 1 2 3 4 16 sout output wclk output tag output lsb left tag lsb right tag 31 32 1 2 3 4 16 msb-1 left data msb-2 lsb msb msb-1 right data msb-2 lsb zeros zeros zeros input l r ck input 17 18 17 18 msb msb msb figure 9. serial data output timing: slave mode, left-justified with no msb delay, s/ m = hl, r l just = lo, msbdly = hl
ad1870 rev. a 15 bclk rdedge = lo bclk rdedge = hi 32 1 2 3 4 17 sout output wclk output tag output msb left tag msb right tag 31 32 1 2 3 4 17 msb-1 left data msb-2 lsb msb-1 right data msb-2 lsb zeros zeros zeros input l r ck input 5 5 msb lsb msb lsb figure 10. serial data output timing: slave mode, i 2 s-justified, s/ m = hl, r l just = lo, msbdly = lo bclk rdedge = lo bclk rdedge = hi 31 32 1 2 15 16 17 18 19 32 1 2 15 16 17 18 19 32 1 2 msb-14 lsb previous data msb-1 left data msb-2 lsb right data sout output zeros zeros msb-1 msb-2 lsb zeros wclk output tag output msb lsb left tag msb lsb right tag msb lsb left tag output l r ck output msb msb figure 11. serial data output timing: master mode, right-justified with no msb delay, s/ m = lo, r l just = hl, msbdly = hl bclk rdedge = lo bclk rdedge = hi 32 1 2 16 17 18 19 1 2 16 17 18 19 20 1 2 msb-14 lsb previous data msb-1 left data msb-2 lsb right data sout output zeros zeros msb-1 msb-2 lsb zeros wclk output tag output msb lsb left tag msb lsb right tag 20 l r ck output output msb msb figure 12. serial data output timing: master mode, right-justified with msb delay, wclk pulsed in 17th bclk cycle, s/ m = lo, r l just = hl, msbdly = lo
ad1870 rev. a 16 bclk rdedge = lo bclk rdedge = hi 31 32 1 2 3 16 sout output wclk output tag output lsb left tag lsb right tag 31 32 1 2 3 16 msb-1 left data msb-2 lsb msb-1 right data msb-2 lsb zeros zeros zeros l r ck output output 17 18 17 18 msb msb msb msb figure 13. serial data output timing: master mode, left-justified with no msb delay, s/ m = lo, r l just = lo, msbdly = hl bclk rdedge = lo bclk rdedge = hi 321234 17 sout output wclk output tag output msb left tag msb right tag 31 32 1 2 3 4 17 msb-1 left data msb-2 lsb msb-1 right data msb-2 lsb zeros zeros zeros output l r ck output msb lsb msb lsb figure 14. serial data output timing: master mode, i 2 s-justified, s/ m = lo, r l just = lo, msbdly = lo bclk rdedge = lo bclk rdedge = hi 31 32 1 2 3 4 16 sout output wclk output tag output 19 20 21 32 1 2 input hi hi 51718 lsb left tag msb lsb right tag left tag lsb msb-14 lsb previous data msb-1 msb-2 msb-3 left data msb-4 msb-3 msb-4 lsb msb-1 msb-2 right data lsb msb-1 left data l r ck input msb msb msb msb msb figure 15. serial data output timing: slave mode, left-justified with no msb delay, 32-bit frame mode, s/ m = hl, r l just = lo, msbdly = hl
ad1870 rev. a 17 bclk rdedge = lo bclk rdedge = hi 32 1 2 3 4 5 17 sout output tag output 20 21 22 1 2 3 input wclk output hi hi 61819 msb left tag msb lsb right tag msb-14 lsb previous data msb-1 msb-2 msb-3 left data msb-4 msb-3 msb-4 lsb msb-1 msb-2 right data lsb msb-1 left data msb left tag msb right tag l r ck input msb lsb msb msb lsb figure 16. serial data output timing: slave mode, i 2 s-justified, 32-bit frame mode, s/ m = hl, r l just = lo, msbdly = lo bclk output (64 x f s ) rdedge = lo clkin input bclk output (64 x f s ) rdedge = hi wclk output data and tag outputs t dlyckb t bpwl t bpwh t bpwl t bpwh t dlyblr t dlydt t dlybwr t dlybwf l r ck output xmit xmit xmit xmit figure 17. master mode clock timing wclk input data and tag outputs xmit t bpwl t bpwh t bpwh t bpwl t dlylrdt msb msb-1 t dlybdt t setlrbs bclk input rdedge = lo bclk output rdedge = hi l r ck input t setwbs sample xmit sample figure 18. slave mode clock timing clkin input reset input t cpwh t cpwl t clkin t rpwl figure 19. clkin and reset timing
ad1870 rev. a 18 outline dimensions r-28 (s-suffix) 28-lead wide-body so sol-28 dimensions shown in inches and (millimeters) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 28 15 14 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.7125 (18.10) 0.6969 (17.70) 0.0118 (0.30) 0.0040 (0.10) ad1870 revision history location page 6/02?ata sheet changed from rev. 0 to rev. a. edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
19
c00944 0 6/02(a) printed in u.s.a. 20

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